EDA Startup Zenasis Unveils "Hybrid Optimization" Technology

AT DESIGN AUTOMATION CONFERENCE (DAC) BOOTH #2357

CAMPBELL, CALIF., April 29, 2002 -- Electronic Design Automation (EDA) newcomer Zenasis Technologies, Inc., today unveiled its "hybrid optimization" technology for high-performance integrated circuit (IC) design.

Currently in limited, pre-beta use with select customers, Zenasis will introduce its products for standard-cell based designs, based on its hybrid optimization technology, early next year. Zenasis was founded in 2000 to bridge the increasing gap between process and design automation technologies. It brings a new dimension to optimization of cell-based designs by breaking the boundary between cell and transistor levels. While physical optimization operates at the placed-gate level using a fixed library of cells, hybrid optimization operates simultaneously at the placed-gate and transistor levels, identifying and creating design-specific cells, and using them to optimize the design. Results are simultaneous gains in speed, power, area, routing congestion and signal integrity.

"Physical synthesis solutions have come a long way in solving the timing closure problem between synthesis and place and route," says Dr. Jay Roy, Zenasis' president and chief executive officer (CEO). "And yet, the design still maps to small cells from a fixed library that limit design quality. This creates designs with too many cells and interconnect wires, problems we believe we can solve."

The Zenasis technology complements existing cell-based synthesis and physical design flows. Until now, IC designers have assumed that performance, power, area and signal integrity are insidious tradeoffs and the wiring explosion is a necessary byproduct of a synthesis methodology.

By merging cells and eliminating wires, the Zenasis' technology can simultaneously improve performance, power, area, signal integrity and reduce the wiring explosion caused by synthesis of large designs in smaller process geometries.

Founders, Management Team
The Zenasis team has extensive experience in the design, marketing and sales of EDA software and hails from within the electronics, semiconductor and EDA industries. Founders are Dr. Jay Roy, Dr. Debashis Bhattacharya and Dr. Vamsi Boppana.

Dr. Roy most recently worked in the microprocessor design division of Sun Microsystems. He co-founded TriQuest Design Automation in 1995 and served as its vice president of engineering. When Summit Design acquired TriQuest in 1997, he served as the vice president of RTL analysis and optimization products.

Dr. Debashis Bhattacharya is chief technology officer (CTO). Previously, he was a member of technical staff at Texas Instruments and taught VLSI Design for seven years at Yale University.

Dr. Vamsi Boppana is principal engineer. Earlier, Dr. Boppana worked for the Advanced CAD Research Group at the Fujitsu Laboratories of America (FLA). He was awarded the Van Valkenburg Fellowship at the University of Illinois for demonstrated excellence in research and Intellectual Property Contribution award from FLA.

Four industry veterans with more than 70 years of combined experience round out the management team. Mark Brown serves as chief software architect. David Crites is director of sales. Ravi Ravikumar is director of marketing. The controller is Robyn Sherman.

Investment, Board of Directors
In a separate announcement, Zenasis today said it has received $6 million in venture financing, led by Sigma Partners. (See accompanying news release.)

Members of the Board of Directors are: Dr. Roy; Dr. Bhattacharya; Faysal Sohail, former CEO of Cadabra Design Automation; Alfred Stein, former CEO of VLSI Technology; and Mark Pine, managing partner of Sigma Partners.

Contacting Zenasis Technologies
To learn more about Zenasis Technologies, visit its website located at: http://www.zenasis.com. Or, contact Ravi Ravikumar at (408) 364-2002, Ext. 111, or via email at ravi@zenasis.com.

Zenasis Technologies will exhibit at the 39th Design Automation Conference (DAC) Monday, June 10, through Wednesday, June 13, at the Ernest N. Morial Convention Center in New Orleans in Booth Number 2357.

About Zenasis Technologies, Inc.
Zenasis Technologies, Inc., is an electronic design automation (EDA) company delivering next-generation IC optimization technology for cell-based design. Its context-specific "hybrid optimization" operates at the gate and transistor levels for a given design placement, and empowers designers to simultaneously improve performance, power, area, signal integrity and routing. The Zenasis team has a mix of experience in EDA, semiconductor and high-performance design industries. Founded in 2000, it has received $7.5 million in a combination of venture and seed financing from Sigma Partners and private seed investors. Corporate headquarters is located at: 1671 Dell Ave., Suite 206, Campbell, Calif., 95008. Telephone: (408) 364-2002. Facsimile: (408) 364-2236. Email: info@zenasis.com. On-line information is found at its website: http://www.zenasis.com.

For more information, contact:
Nanette Collins
Public Relations for Zenasis Technologies
(617) 437-1822
nanette@nvc.com